Description: 数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成
果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用
并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。-NC divider output signal frequency is a function of input data. Using traditional methods of design, process and circuit design are complex and can modify the design of the results are poor and portability. NC VHDL divider based on the design, the whole process simple, fast, easy to modify, strong portability. He can use preset number of parallel addition and subtraction counter counter to achieve. Widely used in electronic equipment, musical instruments and other digital electronic systems. Platform: |
Size: 174080 |
Author:邱颖 |
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Description: 用VHDL语言实现的计时器，最大计时为24小时，计时精度为1ms，设有复位和暂停功能，使用的晶振频率为50Hz。-VHDL language implementation of the timer with a maximum time of 24 hours, timing accuracy of 1ms, with reset, and pause functions, using the crystal oscillator frequency is 50Hz. Platform: |
Size: 3072 |
Author:周峰 |
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Description: 该数字式相位测量仪以单片机 (89c52) 为核心 , 通过高速计数器 CD4040 为计数器计算脉冲个数从 , 而达到计算相位的要求 , 通过 8279 驱动数码管显示正弦波的频率，不采用一般的模拟的振动器产生 , 而是采用单片机产生 , 从而实现了产生到显示的数字化 . 具有产生的频率精确 , 稳定的特点 . 相移部分采用一般的 RC 移相电路 , 节省了成本。-The digital phase-measuring instrument in order to microcontroller (89c52) as the core, high-speed counter CD4040 as counter to calculate the number of pulses from, to achieve the requirements of the calculation phase, through 8279 driving LED display sine wave frequency, non-use of simulation in general vibrators produce, instead of using SCM generation, in order to achieve the creation to display digital. has produced a frequency accuracy and stability characteristics. phase shift part of the application of the normal RC phase-shift circuit, saving costs. Platform: |
Size: 145408 |
Author:包进辉 |
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Description: 基于ep3c25的FPGA频率计的简单设计（用VHDL编写），直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using VHDL written), directly open a can ... ... Platform: |
Size: 1130496 |
Author:yunhen |
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Description: 基于FPGA的频率计设计。通过FPGA运用、 HDL编程，利用FPGA(现场可编程门阵列)芯片设计了一个8位数字式等精度频率计，该频率计的测量范围为0-100MHZ，利用QUARTUS II集成开发环境进行编辑、综合、波形仿真，并下载到CPLD器件中，经实际电路测试，仿真和实验结果表明，该频率计有较高的实用性和可靠性。-Frequency counter FPGA-based design. By using FPGA, VHDL programming, the use of FPGA (field programmable gate array) chip design an 8-bit digital precision frequency meter, etc., the frequency meter measurement range of 0-100MHZ, using QUARTUS II integrated development environment for editing, synthesis, simulation waveforms, and downloaded to the CPLD device, the actual circuit testing, simulation and experimental results show that the frequency counter has a higher availability and reliability. Platform: |
Size: 595968 |
Author:吴亮 |
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Description: VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具，主要应用与同频率正弦信号间的相位差的测量显示。
本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显示译码电路显示，测相范围为 ，相位测量误差 < 。
经测试结果验证，本系统充分利用FPGA对数据的高速处理能力，是系统设计高效、可靠，处理速度快，稳定性高，易于实现。
-VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware description language VHDL system means a description of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u Platform: |
Size: 1367040 |
Author:张学仁 |
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Description: （1） 学习和掌握了解分频电路、通用同步计数器、异步计数器的使用方法；
（2） 理解Moore和Mealy两种状态机的一般编程方法，能够按工程控制需求设计相应的逻辑和时序控制程序。
以开发板上的六盏LED小灯模拟，三盏小灯模拟一个方向的红黄绿交通灯灯，用VHDL语言编程实现红绿交通灯控制程序。
-(1) to learn and master the understanding of frequency division circuit, universal synchronous counter, asynchronous counter to use
(2) to understand Moore and Mealy two state machine of the general programming method, according to engineering control requirements to design the corresponding logic and timing control procedures.
To the development of the six small LED lights on the board simulation, three small lights to simulate a direction of the red, yellow and green traffic lights, using VHDL language programming to achieve red and green traffic light control program. Platform: |
Size: 602112 |
Author:Cherry_RF |
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Description: （1） 学习和掌握了解分频电路、通用同步计数器、异步计数器的使用方法；
（2） 理解Moore和Mealy两种状态机的一般编程方法，能够按工程控制需求设计相应的逻辑和时序控制程序。
以开发板上的六盏LED小灯模拟，三盏小灯模拟一个方向的红黄绿交通灯灯，用VHDL语言编程实现红绿交通灯控制程序。
-(1) to learn and master the understanding of frequency division circuit, universal synchronous counter, asynchronous counter to use
(2) to understand Moore and Mealy two state machine of the general programming method, according to engineering control requirements to design the corresponding logic and timing control procedures.
To the development of the six small LED lights on the board simulation, three small lights to simulate a direction of the red, yellow and green traffic lights, using VHDL language programming to achieve red and green traffic light control program. Platform: |
Size: 64512 |
Author:Cherry_RF |
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Description: 电子琴 原创 作业 VHDL 采用计数器分频，内含简单儿歌数首，爱迪克ＥＤＡ实验箱，有数码管与ＬＥＤ显示，采用键盘式输出，两行，中音高音。(Electronic piano original work VHDL, using counter frequency division, contains a few simple nursery rhyme, Edik EDA experimental box, there are digital tube and LED display, using keyboard output, two lines, alto treble.) Platform: |
Size: 1101824 |
Author:qengleikangjen
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Search - a frequency counter using VHDL